芯片架构师(北京/深圳)
Core
Designing and optimizing SoC architecture, including bus topology, QoS strategies, address translation, memory access behavior, and IO device-CPU cache consistency.
Role type
Senior IC SoC Architect
Builds
High-performance System-on-Chip (SoC) systems and accelerator IPs
Domain
Semiconductor / SoC Design
Required skills
SoC architecture design, bus topology optimization, cache behavior and performance tuning, DRAM performance optimization, IO consistency access optimization, QoS strategy formulation, accelerator IP memory subsystem design, hardware scheduling, interrupt aggregation, PPA optimization, CPU interrupt and memory access behavior understanding, cache coherence and memory consistency knowledge
Preferred skills
Advanced process node experience (200mm2+), subsystem-level PPA and delivery ownership
Technologies
SoC, Bus Topology, Cache, DRAM, QoS, Accelerator IP, PPA
Responsibilities
Define SoC architecture schemes including bus topology, QoS, address translation, and memory access behavior; Optimize SoC performance including bus data paths, DDR access, and IO consistency paths; Define memory subsystem and hardware scheduling behaviors for accelerator IPs; Establish and optimize PPA metrics for SoC and accelerator IPs
Seniority
Senior, hands-on IC
