芯片综合/STA工程师（芯片平台） - 芯片研发
Core
Perform logic synthesis, formal verification, and STA signoff for SoC chips, collaborating on clock/reset, low power, and timing convergence strategies.
Role type
IC design engineer (logic synthesis & STA)
Builds
SoC chips
Domain
Semiconductor / IC Design
Required skills
Logic synthesis, Static Timing Analysis (STA), Formal verification, Scripting (TCL, Perl, Python), EDA tools (DC, PT, Formality, LEC, Tempus), SoC DFT
Preferred skills
SoC DFT experience
Technologies
DC, PT, Formality, LEC, Tempus, SDC
Responsibilities
Perform logic synthesis, formal verification, and STA signoff; Collaborate on clock/reset and low power solutions; Ensure timing convergence before tape-out.
Seniority
Mid-level, hands-on IC engineer
