混合信号/高速接口ASIC设计工程师（芯片平台） - 芯片研发
Core
Design high-speed interface IP for silicon front-end, covering architecture modeling, RTL implementation, and post-silicon test analysis.
Role type
Senior IC mixed-signal/high-speed interface ASIC engineer
Builds
High-speed interface IP blocks for chip platforms
Domain
Semiconductor / High-speed digital interfaces
Required skills
Verilog, high-speed interface IP design, mixed-signal IP design, computer architecture, AMBA protocols, scripting (TCL/Perl/Python)
Preferred skills
UCIe, DDR, PCIe, UAlink experience, SerDes modeling and architecture evaluation
Technologies
Verilog, AMBA, TCL, Perl, Python, Makefile
Responsibilities
Model and analyze high-speed interface IP architecture, implement high-speed interface IP in digital RTL, perform post-silicon testing for high-speed interface IP
Seniority
Senior, hands-on IC
