硬件开发-AI核设计方向(北京/上海/深圳)
Core
Designing AI core microarchitecture, RTL implementation, timing analysis, and PPA optimization for AI chips.
Role type
Senior IC hardware design engineer (AI core)
Builds
AI accelerator chips
Domain
Semiconductor / AI hardware
Deliverable
production ML models
Required skills
Microarchitecture design, RTL design (Verilog/VHDL), Timing analysis, PPA optimization, ASIC/FPGA design flow, EDA tools (Cadence/Synopsys), Digital circuit design, Processor architecture, Memory interfaces, Bus interfaces
Preferred skills
C/C++, Python, System integration, Documentation, Performance analysis, Chip simulation and debugging
Technologies
Verilog, VHDL, C, C++, Python, Cadence, Synopsys, Mentor Graphics
