DTCO负责人（存算与AI） - 芯片研发
Core
Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing foundation for AI large models.
Role type
Senior DTCO Engineer (Backend Devices & Architecture)
Builds
High-efficiency AI chips using in-memory computing architecture
Domain
Semiconductor design, AI hardware, Backend-of-Line (BEOL) device engineering
Deliverable
production ML models
Required skills
TCAD simulation, SPICE modeling, Verilog-A, Python, PDK modeling, storage array testing, parasitic extraction, reliability assessment (BTI), yield prediction, cross-disciplinary DTCO optimization
Preferred skills
Embedded storage yield improvement, EDA tool flow establishment, circuit-array performance trade-off analysis
Technologies
TCAD, SPICE, Verilog-A, Python
Responsibilities
Characterize physical properties of new BEOL devices, develop SPICE models and PDKs, analyze storage arrays for parasitics and reliability, establish array-level reliability and crosstalk analysis methods, perform high-sigma statistical analysis for yield prediction, optimize system performance and power consumption at circuit and array levels
Seniority
Senior, hands-on IC
