ASIC Packaging SI/PI Engineer (Hybrid)
Core
Develop, document, and implement design rules for ultra-high-speed signaling and analyze substrate signal and power integrity (SI/PI) for next-generation ASIC packaging.
Role type
Senior IC ASIC Packaging SI/PI Engineer
Builds
High-performance Silicon ASICs for unified routing and switching platforms (TOR switches to web-scale data centers)
Domain
Semiconductor / High-Speed Digital Design / Advanced Packaging
Required skills
High-speed design theory (Transmission Line, electromagnetics, S-parameters), SI/PI simulation and validation, EDA tools (Cadence Sigrity, Ansys HFSS, Keysight ADS), Measurement planning and execution (VNA, TDR, oscilloscopes), Debug and tooling for high-speed systems
Preferred skills
High-bandwidth memory (HBM) interface SI, Die-to-die interfaces (UCIe), Advanced packaging (CoWoS, EMIB, 2.5D), Test plan execution for high-speed interfaces, S-parameter and crosstalk analysis
Technologies
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, VNA, TDR, Oscilloscopes, Spectrum analyzers, Network analyzers, Probe stations
Responsibilities
Develop and implement design rules for ultra-high-speed signaling; Analyze substrate SI/PI and collaborate with layout teams; Design and document ASIC packages for high-volume release; Collaborate with system partners to resolve complex technical issues
Seniority
Senior, hands-on IC
