Senior Mask Design Engineer - Hardware
Core
Performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
VLSI products
Domain
Semiconductor hardware design
Required skills
Mixed-signal circuit layout, Cadence Virtuoso, DRC/LVS flows, Perl/Python scripting, Verification tools (Dracula, Hercules, Calibre, Primeyield)
Preferred skills
None stated
Technologies
Cadence Virtuoso, Dracula, Hercules, Calibre, Primeyield, Perl, Python
Responsibilities
Perform physical layout for mixed-signal functions, work cross-functionally with ASIC engineers, take part in floor planning and custom layout, verify against design rules and schematics
Seniority
Senior, hands-on IC
