MTS Mask Design Engineer
Core
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, specifically verifying mask designs against leading edge physical and electrical checks.
Role type
Senior IC Mask Design Engineer
Builds
Integrated circuits (SOC level macros and tiles) for semiconductor manufacturing
Domain
Semiconductor / Hardware Design
Required skills
IC Mask Layout Design, Analog and RF/High-Speed design, Cadence Design environment, Virtuoso XL/EXL/MXL, Calibre verification tools, DRC/LVS debug, Advanced layout techniques (16nm and below), Floorplanning, IR drop and Isolation techniques
Technologies
Virtuoso, Calibre, Cadence
Responsibilities
Verify mask designs against physical and electrical checks, oversee mask designs for complex macros and tiles, contribute to design flow including DRC/LVS debug and EM/IR analysis, drive projects of significant technical importance
Seniority
Senior, hands-on IC
