Heterogeneous Integration Physical Design Engineer
Core
Define, model, design, optimize, verify, validate, and document IP (block/SoC) development for high-performance, low-power products, with a focus on 2.5D/3D heterogeneous integration and System-Technology Co-Optimization (STCO).
Role type
Senior IC physical design engineer (heterogeneous integration)
Builds
2.5D/3D chiplet integration solutions (SoIC, CoWoS, hybrid bonding, interposer, RDL), custom DRAM/3D SRAM integration, and test-chip designs.
Domain
Semiconductor / Advanced Packaging / ASIC Design
Required skills
2.5D/3D heterogeneous integration, physical design, custom layout, hybrid bonding, wafer bonding, TSV, micro-bump/u-bump, RDL, backside metallization, PDK development, DRC, LVS, PEX, DFM, Calibre, Cadence, SVRF, TCL scripting, test-chip design, mask layout, tapeout, PPAC assessment, system PDN, Power Integrity (PI), Signal Integrity (SI), process integration, 3D cache/SRAM architecture.
Preferred skills
TSMC SoIC/CoWoS product development, process integration, unit process development, 3D cache/SRAM partitioning.
Technologies
Calibre, Cadence, SVRF, TCL, SoIC, CoWoS, TSMC
Responsibilities
Drive PPAC assessment and technology pathfinding for STCO and heterogeneous integration; Evaluate and develop 2.5D/3D chiplet integration solutions; Perform custom DRAM and 3D SRAM integration evaluation; Develop and support test-chip design, mask layout, design flows, and PDK enablement; Perform layout and design analysis for benchmarking, DFM, and debugging; Develop and assess advanced system PDN solutions; Serve as technical interface with foundries.
Seniority
Senior, hands-on IC
