Distinguished Signal and Power Integrity Engineer
Core
Lead corporate-level strategies and technical direction for high-speed signaling, interconnect, and advanced semiconductor packaging solutions for next-gen AI, HPC, and ultra-mobile platforms.
Role type
Distinguished Signal and Power Integrity Engineer (Strategy & Architecture)
Builds
State-of-the-art interconnect and packaging solutions (UCIe, HBM, DDR, PCIe, SerDes), co-packaged optics, stacked die, and chiplet-based architectures.
Domain
Semiconductor industry, high-speed signaling, computational electromagnetics, advanced packaging.
Required skills
High-speed signal integrity, computational electromagnetics, semiconductor assembly technologies, advanced packaging (EMIB, UCIe, CPO), high-density connectors, modeling and characterization flows, design for high volume manufacturing, team leadership, strategic technology investment.
Preferred skills
Industry veteran track record, pioneer in high-speed signaling standards, deep knowledge of package substrate/PCB/cable/connector manufacturing challenges.
Technologies
UCIe, HBM, DDR, PCIe, SerDes (224G/448G), EMIB, CPO, IVR.
Responsibilities
Lead development of corporate strategies for high-speed signaling; oversee technical direction for next-gen products; architect interconnect and packaging solutions; enable advanced packaging technology solutions; develop modeling and characterization flows; offer strategic counsel to senior leadership.
Seniority
Distinguished, hands-on IC with strategic leadership
