PLL Design Engineer
Core
Design complex building blocks of Phase Locked Loops (PLL) including architecture development and transistor-level circuit design for AMD processors.
Role type
Senior IC mixed-signal circuit design engineer (PLL)
Builds
Advanced PLL IPs powering AMD processors
Domain
Semiconductor / Analog Mixed-Signal Design
Required skills
Mixed Signal Circuit Design, FinFET technology, PLL architecture, VCO design, Charge-pump design, Divider design, State machines, LDO design, Bandgap reference, TDC circuits, Interpolator circuits, High-speed buffers, Analog circuit design methodology, Physical design basics, STA, Tcl scripting, Perl, Python
Preferred skills
FinFET & Dual Patterning nodes (3nm/2nm/A14), Digital PLL techniques, Control theory, Fractional-N PLLs, Spread-spectrum PLLs, Cadence ADE-L/ADE-XL, Monte-Carlo/Noise/Aging/EM/IR drop simulations, Spectre/Hspice/AFS/MATLAB, System Verilog, DRC/LVS verification, Calibre/ICV tools
Technologies
Cadence ADE-L, Cadence ADE-XL, Spectre, Hspice, AFS, MATLAB, System Verilog, Python, Perl, Tcl, Calibre, ICV
Responsibilities
Design complex building blocks of a PLL including architecture development and transistor level circuit design, Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements, Work closely with mask design engineers to deliver the physical design and define test plans, Lead/mentor junior engineers
Seniority
Senior, hands-on IC
