Physical Design and Verification Engineer
Core
Senior Physical Design Engineer owning block-to-full-chip implementation and multi-physics verification (thermal, mechanical, IR/EM) for advanced-node 3DIC products.
Role type
Senior IC physical design engineer (3DIC)
Builds
Advanced-node multi-die 3DIC products (stacked-die and chiplet-based systems)
Domain
Semiconductor / 3D Integrated Circuits
Required skills
Hierarchical physical design, floorplanning, placement, CTS, routing, static timing analysis (STA), physical verification (DRC/LVS), EM/IR analysis, TCL scripting, advanced node RTL-to-GDSII flow
Preferred skills
3DIC/2.5D/chiplet implementation (TSVs, µbumps, hybrid bonding), multi-physics analysis (thermal, mechanical, stress), Python scripting, reliability signoff (EM, aging, ESD)
Technologies
Cadence Innovus/Genus/Tempus/Voltus, Synopsys ICC2/Fusion Compiler/PrimeTime/StarRC, Siemens Calibre, Ansys RedHawk-SC, Cadence Voltus/Celsius/Integrity 3D-IC, Synopsys 3DIC Compiler
Responsibilities
Define hierarchical partitioning strategies and manage die-to-die partitioning for 3D stacks; execute synthesis, floorplanning, placement, CTS, and routing; perform static timing analysis and physical verification signoff; build and run thermal models and perform mechanical/warpage analysis; correlate thermal, mechanical, and electrical effects; develop and automate PnR and signoff flows; partner with packaging, DFT, and DV teams
Seniority
Senior, hands-on IC
