Stage Ingénieur : Développement d’un outil d’analyse de performance pour simulations hardware (H/F)
Core
Develop an internal tool to extract and measure performance indicators from hardware simulations of digital components to facilitate test scenario analysis and identify optimization points.
Role type
Junior IC hardware verification engineer (intern)
Builds
Internal performance analysis tool for hardware simulation environments
Domain
Semiconductor hardware design and verification (SoC, digital components)
Required skills
Digital design and verification flow, VHDL/Verilog/SystemVerilog, Python, Linux environment, Bash/Tcl scripting
Preferred skills
UVM, simulation trace analysis, system performance analysis
Technologies
Python, VHDL, Verilog, SystemVerilog, Linux, Bash, Tcl, UVM
Responsibilities
Understand existing hardware simulation environment, Identify relevant performance metrics (latency, bandwidth, waiting time), Define data collection and processing format, Develop tool to automatically analyze simulated system performance, Generate reports or synthetic views to compare simulation scenarios, Integrate tool into existing verification environment, Validate solution on representative use cases
