Stage ingénieur : Analyse de la consommation et optimisation des tests pour les System-on-Chip (SoC) de nouvelle génération (H/F)
Core
Analyzing power consumption and test quality for next-generation System-on-Chip (SoC) designs to bridge pre-silicon predictions with post-silicon measurements.
Role type
Intern, Design-for-Test (DFT) Engineer
Builds
Next-generation semiconductor SoC products
Domain
Semiconductor industry, Digital Design, Data Science
Deliverable
production ML models
Required skills
Python programming, Artificial Intelligence, Digital design, Test methodologies (DFT, ATPG, JTAG, BIST), Data analysis
Preferred skills
Scan insertion, Scan compression, Power-aware testing, Hardware emulation platforms
Technologies
Python, EDA tools, Simulation platforms, Hardware emulation
Responsibilities
Discovering DFT methodologies for complex SoCs, Executing and analyzing DFT test scenarios on emulation platforms, Investigating test power consumption and metrics, Analyzing large datasets from simulations and silicon characterization, Applying AI to identify patterns and anomalies, Developing automation solutions for reporting
Seniority
Intern
