Stage ingénieur : Analyse de la consommation et optimisation des tests pour les System-on-Chip (SoC) de nouvelle génération (H/F)
Core
Analyzing power consumption and optimizing test quality for next-generation System-on-Chip (SoC) designs using AI and automation.
Role type
Intern, SoC Design-for-Test (DFT) Engineer
Builds
Next-generation semiconductor products (automotive, industrial, IoT)
Domain
Semiconductor / SoC Design / Test Engineering
Deliverable
production ML models | product features
Required skills
Python programming, AI/ML techniques, Digital design fundamentals, Test coverage analysis, Hardware emulation, Data analysis
Preferred skills
Scan insertion/compression, ATPG, JTAG, BIST, Power-aware testing, Silicon characterization
Technologies
Python, EDA tools, Hardware emulation platforms, Simulation tools
Responsibilities
Discover DFT methodologies (scan, ATPG, JTAG, BIST), analyze test power consumption, evaluate test coverage and fault models, apply AI to detect anomalies in test data, develop automation scripts for reporting, collaborate with physical design and validation engineers.
Seniority
Intern (Master's level)
