Intern – DRAM Technology Physical Design and Block-Level PPA Optimization
Core
Intern role optimizing power, performance, and area (PPA) for advanced memory products at the standard cell and logic block level.
Role type
Intern, physical design and PPA optimization
Builds
Standard cell logic blocks and optimized memory designs
Domain
Semiconductor / Memory / Physical Design
Deliverable
production ML models
Required skills
VLSI design concepts, ASIC physical design flow, scripting (Python/Perl/TCL), static timing analysis (STA), physical verification (DRC/LVS/IR-drop), Generative AI/AI automation
Preferred skills
Place-and-route tools (Synopsys ICC2, Cadence Innovus), timing verification tools (PrimeTime, Tempus), design constraints (SDC), LEF/DEF formats, low-power design (UPF/CPF), AI/LLM application
Technologies
Synopsys ICC2, Cadence Innovus, PrimeTime, Tempus, Python, Perl, TCL, UPF, CPF, SDC
Responsibilities
Implement standard cell logic blocks using physical design tools (floorplanning, placement, CTS, routing), analyze and benchmark PPA across libraries, perform static timing analysis and support timing closure, execute physical verification checks (DRC, LVS, IR-drop), leverage AI tools to automate data collection and workflow optimization
Seniority
Intern
