Stage Ingénieur : Application de l'Intelligence Artificielle à l'intégration de blocs RTL (ASIC/FPGA) (H/F)
Core
Develop an AI-based solution to automate and improve the reliability of RTL IP integration within ASIC and FPGA projects.
Role type
Final-year engineering intern (AI for hardware design)
Builds
AI-powered analysis tools and scripts for RTL integration
Domain
Semiconductor / Digital Hardware Design
Deliverable
production ML models | product features
Required skills
RTL design, Verilog/SystemVerilog/VHDL, Python/Perl scripting, Linux environment
Preferred skills
Hardware communication protocols (AXI, APB, AHB), ASIC/FPGA simulation/synthesis tools, AI in engineering
Technologies
Python, Perl, Linux, Verilog, SystemVerilog, VHDL, AXI, APB, AHB
Responsibilities
Study RTL integration challenges in ASIC/FPGA, analyze current integration flows, implement AI mechanisms for automatic parameter and interface detection, develop a prototype integration assistance tool, validate the solution on real IP blocks
Seniority
Intern (Final-year engineering student)
