ASIC Engineer Intern
Core
Develop automation infrastructure for next-generation ASIC devices used in optical communications.
Role type
ASIC Engineer Intern
Builds
Automation infrastructure for large-scale DSP ASICs
Domain
Optical communications / Semiconductor design
Deliverable
production ML models | product features | infrastructure
Required skills
Python, SystemVerilog, UVM, TCL, Skill/Ocean, Linux development
Preferred skills
ASIC/FPGA development, analytical debugging, Agile/JIRA/Git
Technologies
SystemVerilog, UVM, Python, TCL, Skill, Ocean, Linux
Responsibilities
Develop design blocks and evaluate designs for correctness and performance; Implement netlists into silicon-realizable layouts and automate placement and extraction workflows; Create constraints, analyze implementation reports, and automate ASIC integration processes; Develop reusable SystemVerilog/UVM verification components; Enhance Python-based reporting, analysis, build, simulation, and debug workflows.
Seniority
Intern
