Staff ENGINEER, HIG HBM-ARCHITECTURE
Core
Define and implement end-to-end DFT architectures for HBM base die and DRAM die to ensure quality, yield, and performance across complex multi-die architectures.
Role type
Staff IC HBM Design Architect (DFT)
Builds
3D-stacked memory products (HBM) for data centers and AI applications
Domain
Semiconductor manufacturing / Memory / 3D-stacked integration
Required skills
DFT architecture, scan/MBIST/JTAG/boundary scan, wafer probe and final test flows, silicon observability, cross-functional collaboration, AI for design quality
Preferred skills
HBM/DRAM/advanced memory product experience, TSV-based 3D integration knowledge, at-speed test techniques, DFT security features, AI for DFT coverage improvement
Technologies
JTAG, MBIST, TSV, 3D-stacked memory
Responsibilities
Define and implement end-to-end DFT architectures for HBM base die and DRAM die; Develop DFT strategies for stacked-die, cube-level, and system-level test flows; Architect test access mechanisms supporting wafer probe through final test; Enable silicon observability for yield learning, debug, and failure analysis; Collaborate across design, verification, layout, test, and manufacturing teams; Leverage AI for design quality improvement and DFT
Seniority
Staff, hands-on IC
