STA - CAD Engineer
Core
Develop and deploy timing analysis (STA) methodologies and flows for next-generation AMD processor designs across embedded, server, desktop, and laptop segments.
Role type
Senior IC STA Engineer (Timing Analysis)
Builds
Timing closure flows and EDA tool capabilities for silicon design
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
production ML models
Required skills
STA methodologies, STA signoff tools, extraction tools, placement and routing tools, timing report analysis, Verilog, System Verilog, 3DIC design, EDA tool competence, scripting (Perl, Python, TCL), UNIX
Preferred skills
Machine learning for EDA workflows, data preprocessing, feature engineering, model evaluation, ML tool integration, technical documentation, global team collaboration
Technologies
Perl, Python, TCL, UNIX, Verilog, System Verilog
Responsibilities
Develop timing methodology flows, release high-quality flows, support design teams on critical issues, evaluate and qualify new EDA tools, collaborate on ML models for EDA workflows, automate design verification and analysis, integrate ML tools into CAD infrastructure
Seniority
Senior, hands-on IC
