Staff ENGINEER, HIG HBM-ARCHITECTURE
Core
Define and implement end-to-end DFT architectures for next-generation HBM base die and DRAM die to ensure quality, yield, and performance across complex multi-die architectures.
Role type
Staff IC HBM Design Architect
Builds
Test architectures for 3D-stacked memory products
Domain
Semiconductor manufacturing and memory storage (via careerplan.io/jobs/JR113291-staff-engineer-hig-hbm-architecture-at-micron)
Required skills
DFT architecture design, scan/MBIST/JTAG/boundary scan concepts, wafer probe and final test semiconductor flows, silicon observability, cross-functional collaboration, AI for design quality improvement
Preferred skills
HBM/DRAM/advanced memory product experience, TSV-based 3D integration knowledge, at-speed test techniques, DFT security features, custom customer test interfaces
Technologies
HBM, DRAM, TSV, JTAG, MBIST, wafer probe, AI tools
Responsibilities
Define DFT strategies for stacked-die, cube-level, and system-level test flows; Architect test access mechanisms supporting wafer probe through final test; Enable silicon observability for yield learning, debug, and failure analysis; Collaborate across design, verification, layout, test, and manufacturing teams; Leverage AI for design quality improvement and DFT
Seniority
Staff, hands-on IC
