Sr. Principal IC Digital Flow AE
Core
Senior Application Engineer providing technical support and guidance for Cadence's digital implementation and signoff tools (Synthesis, P&R, Signoff) to help customers achieve PPA targets and design closure.
Role type
Senior IC Application Engineer (Digital Implementation & Signoff)
Builds
IC digital implementation flows and backend EDA tool solutions for semiconductor customers
Domain
Semiconductor / Electronic Design Automation (EDA)
Required skills
Digital Design Fundamentals, Static Timing Analysis, Place and Route, Design Closure, timing/power signoff, IR Drop, advanced nodes (10nm and below), Tcl/Perl/Python scripting, customer-facing communication
Preferred skills
Front-end EDA tools (Synthesis, DFT, LEC), Cadence tools (Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC, DC, Primetime), advanced nodes (5nm and below)
Technologies
Cadence Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC, DC, Primetime, Tcl, Perl, Python
Responsibilities
Provide technical support for Backend Digital Design Implementation and Signoff; Guide customers on tool utilization to meet project schedules; Conduct technical presentations and product demonstrations; Drive technical evaluations and benchmarks; Collaborate with R&D to enhance tools and methodologies; Provide guidance to amend and augment flows using scripting; Capture best practices from evaluations to improve future engagements
Seniority
Senior, hands-on IC
