Design Engineering Manager
Core
Leading pre-silicon physical layer electrical validation infrastructure development and post-silicon validation efforts for High Speed SERDES Test chips.
Role type
Design Engineering Manager (Post Silicon Physical Layer Electrical Validation)
Builds
Hardware and software architecture for test chips, test PCBs, FPGA platforms, and automation scripts for compliance testing.
Domain
Electronic design, High Speed SERDES protocols, Physical Layer Electrical Validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Post-Silicon Physical Layer Electrical Validation, High Speed SERDES protocols (PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO), Lab equipment operation (Oscilloscopes, Network Analyzer, BERT), Hardware/Software architecture design, Test plan definition, Test report generation
Preferred skills
Team management, Full project leadership, FPGA Design, PCB schematic and layout design, Prototyping, Pre-Silicon IP/SoC Physical Layer Electrical Validation, Verilog RTL coding, FPGA coding, Labview, Python, C/C++, TCL, Analog and digital electronic circuit design, Signal processing
Technologies
PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO, FPGA, Labview, Python, C/C++, TCL, Verilog RTL, Oscilloscopes, Network Analyzer, BERT
Responsibilities
Designing hardware and software architecture for test chips and test PCBs, Defining test plans for compliance testing, Implementing tests according to plans, Generating high quality test reports, Leading pre-silicon infrastructure development, Leading post-silicon validation efforts
Seniority
Manager, hands-on IC with team leadership