HBM SOC Design Engineer
Core
Design and development of next-generation HBM DRAM products, focusing on SOC architecture, RTL logic, IP integration, and high-speed interface design.
Role type
Senior IC SOC Design Engineer
Builds
High-performance HBM memory products for data centers and AI/ML workloads
Domain
Semiconductor / Memory & Storage / High-Performance Computing
Deliverable
production ML models | product features
Required skills
SOC Architecture, RTL Logic Design (System Verilog), IP Integration, High-speed interface design, 2.5D & 3D package integration, Microarchitecture, Static timing analysis, Clock domain crossings (CDC), SOC interconnects (AMBA AXI, ACE, APB, AHB), Design for testability (MBIST, scan)
Preferred skills
Python scripting, UCIE IP, Memory Controller IP, NOCs IP
Technologies
System Verilog, Python, AMBA AXI, ACE, APB, AHB, MBIST, 2.5D, 3D
Responsibilities
Analyze customer requirements and select or custom-design off-the-shelf IPs; Review architectural specifications and provide feedback; Develop RTL, integrate IP, test code, and debug failures; Identify and resolve quality, performance, and power issues in architecture and circuits; Debug pre-silicon and post-silicon issues in HBM products.
Seniority
Mid-level, hands-on IC
