Lead Design Engineer
Core
Lead Design Engineer responsible for functional verification environment development, strategy definition, and deployment for electronic design automation tools.
Role type
Senior IC functional verification engineer
Builds
Functional verification environments and methodologies for electronic design automation software
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
production ML models | product features
Required skills
Functional verification fundamentals, UVM methodology, Verilog, SystemVerilog, assertion development, constraint randomization, functional coverage, RTL debug, GLS debug
Preferred skills
Serial bus multiprotocol PHY IP (SerDes, USB/DPHY, UCIe), formal verification, gate-level simulation, power-aware RTL setup
Technologies
UVM, Verilog, SystemVerilog, SerDes, USB, DPHY, UCIe
Responsibilities
Develop and maintain functional verification environments; Define verification strategies and architect environments; Interface with RTL, physical design, and analog design teams; Contribute to new verification methodologies; Support customers with design issues
Seniority
Senior, hands-on IC
