Sr Principal Design Engineer
Core
Design and support RTL for DDR Memory Controller IP solutions, including DDR4/LPDDR4 protocols.
Role type
Senior IC RTL Design Engineer (Memory Controller IP)
Builds
DDR Memory Controller IP cores for semiconductor customers
Domain
Semiconductor / VLSI / Memory Protocols
Deliverable
production ML models | product features
Required skills
RTL design, Verilog, System Verilog, UVM, complex protocol implementation, LINT/CDC design guidelines
Preferred skills
AXI3/4, IP development team experience, DDR Memory controller expertise
Technologies
Verilog, System Verilog, UVM, LINT, CDC
Responsibilities
Design and support RTL for DDR Memory Controller solutions, add new features to existing RTL, ensure design cleanliness for LINT and CDC guidelines, support customer configurations
Seniority
Senior, hands-on IC
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