Lead FrontEnd Methodology Engineer
Core
Maintaining and upgrading infrastructure and automation for RTL development and design-verification teams across multiple server farms and cloud environments.
Role type
Senior IC infrastructure and automation engineer (RTL/verification)
Builds
Automated regression pipelines, error/defect reporting systems, and toolchain infrastructure for chip design teams
Domain
Semiconductor EDA / Chip Design Verification
Deliverable
infrastructure
Required skills
Perl, Python, LSF/Grid/PBS/Open Lava batch queuing, REST API integration, Linux OS migration, SQL (MariaDB/PostgreSQL), Jenkins management, Git/GitHub, TCL scripting, Verilog/SystemVerilog, Cloud deployment (AWS/Azure/IBM)
Preferred skills
Electrical/Computer Engineering degree, 7+ years experience, OVM/UVM methodologies, DPI/PLI models, NFS/memory/CPU profiling, NIS/DNS/LDAP/SMTP/syslog/cron, module-files/modulecmd
Technologies
Perl, Python, SCons, LSF, Grid, PBS, Open Lava, Jenkins, MariaDB, PostgreSQL, Apache, PHP, Javascript, jQuery, AWS, Azure, IBM Cloud, Git, GitHub, Verilog, SystemVerilog, TCL, NFS, NIS, DNS, LDAP, SMTP, syslog, cron, modulecmd
