Senior/Staff Engineer, Technical Manager (Design Verification)
Core
Design verification engineering for Module, IP, and SOC levels using coverage-driven methodologies.
Role type
Senior/Staff Design Verification Engineer
Builds
Verification environments, testbenches, and verification IP
Domain
Semiconductor hardware design verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, SystemVerilog, Verilog, SystemC, randomization, coverage closure, low power verification, formal verification
Responsibilities
Develop and review test plans, Develop verification environment/testbench, Develop verification IP and reference model, Implement test with randomization based coverage driven verification methodology, Implement functional and functional/code coverage closure, Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC
