ASIC设计工程师-AI芯片
Core
Design microarchitecture, RTL, and integration for ASIC chips in data centers, optimizing Power/Performance/Area (PPA) for AI accelerators.
Role type
Senior IC ASIC design engineer (AI accelerators)
Builds
AI accelerator chips
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
RTL design, Verilog, microarchitecture design, PPA optimization, IC design flow, integration of IP blocks
Preferred skills
16nm or advanced process tape-out experience, CPU/NoC/HPC design, DDR/PCIe protocols, synthesis/FV/CLP/STA, AI algorithms (vision/NLP/speech)
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