RTL Design & Integration Engineer (On-site. Bengaluru, India)
Core
Integrate internal and external IPs into top-level System-on-Chips (SoCs) for ultra-low-power, brain-inspired wearable compute systems.
Role type
Senior RTL Design & Integration Engineer (SoC/ASIC)
Builds
Next-generation low-power wearable and implantable devices using Wi-R technology
Domain
Semiconductor hardware design, low-power SoC/ASIC development, wearable computing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (Verilog/SystemVerilog), SoC/IP integration, AXI/AHB/APB protocols, EDA tools (Synopsys Design Compiler, Spyglass), flow automation scripting (Python/Perl/Tcl), synthesis and timing analysis
Preferred skills
Low-power design methodologies (UPF/CPF), custom EDA automation frameworks, high-performance compute architectures
Technologies
Verilog, SystemVerilog, AXI, AHB, APB, Synopsys Design Compiler, Spyglass, Python, Perl, Tcl
Responsibilities
Perform RTL integration of IPs and subsystems into top-level SoCs; Develop and maintain RTL wrappers, interconnect logic, and clock/reset infrastructures; Run lint, CDC, and early synthesis checks; Debug simulation and synthesis issues at block and chip levels; Maintain and automate integration flows; Contribute to design reviews and document integration flows
Seniority
Mid-to-Senior, hands-on IC
