ASIC设计工程师（Scale up内存语义方向） - 芯片研发
Core
Designing ASIC chips for datacenter scenarios, focusing on scale-up memory semantics and high-speed interconnects to optimize performance and reduce costs for ByteDance's business.
Role type
Senior IC ASIC Design Engineer (Scale-up Memory Semantics)
Builds
Custom hardware accelerators and network chips (NICs) for datacenter workloads
Domain
Semiconductor / Datacenter Infrastructure / High-Speed Networking
Deliverable
production ML models
Required skills
ASIC front-end design, Verilog, Scale-up architecture, Load/Store/Atomic memory semantics, RDMA protocol, Computer architecture (MAC, PCIe, AMBA), DDR/HBM interfaces, Scripting (TCL/Perl/Python)
Preferred skills
RDMA pre-research and paper publication, Network chip (NIC/Switch) tape-out experience, AI training parallelism and accelerator architecture, High-speed network cabling and congestion control, RDMA kernel/user-space drivers
Responsibilities
Perform requirement analysis and micro-architecture design for datacenter ASICs; Develop RTL and support verification/integration; Research high-speed interconnect trends and model protocol performance; Conduct software-hardware co-optimization and chip modeling for network cards; Participate in chip testing and risk analysis.
