ASIC设计工程师-AI芯片
Core
Design microarchitecture, RTL, and integration for ASIC chips in data centers, optimizing Power/Performance/Area (PPA) for AI accelerators.
Role type
Senior IC ASIC Design Engineer (AI Chips)
Builds
AI accelerator chips for data centers
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
RTL design, Verilog, microarchitecture design, PPA optimization, IC design flow, verification support
Preferred skills
7nm or advanced process tape-out, CPU/NoC/HPC design, DDR/PCIe protocols, AMBA bus standards, synthesis/FV/CLP/STA, ISP/display design, AI algorithms (vision/NLP/speech)
Technologies
Verilog, AMBA, DDR, PCIe
Responsibilities
Design microarchitecture and RTL for data center ASICs; Optimize PPA and design flow for AI accelerators; Support verification and development of AI chips
Seniority
Mid-Senior, hands-on IC
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