Senior RTL Design Engineer (On-site. Bengaluru, India)
Core
Architect and design ultra-low-power digital systems and control/data path blocks for next-gen wearables using patented Wi-R technology.
Role type
Senior RTL Design Engineer (SoC)
Builds
Communication SoCs for wearable and implantable devices
Domain
Consumer electronics / Wearables / Low-power digital design
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/VHDL), CDC/DRC flows, MBIST/DFT integration, STA/PNR tools, hardmacro integration, power-aware simulation (UPF), ASIC ECO flows
Preferred skills
AMS chip design experience, DSP/wireless circuit knowledge, scripting (Tcl/Perl/Python), low-power design expertise
Technologies
VCS-NLP, UPF, STA, PNR, Wi-R
Responsibilities
Micro-architect and optimize RTL for control and data path blocks; Lead digital block design efforts; Perform RTL linting, simulation, and verification; Integrate hardmacros and ensure timing closure; Collaborate on ECOs and low-power verification flows
Seniority
Senior, hands-on IC
