Hardware Verification
795 open positions
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Staff Design Automation Engineer↗ Skyworks SolutionsKA, IN 12d Build Python-based web platforms and automation tools to modernize RF/AMS module packaging and back-end IC wafer flows, replacing legacy spreadsheet/VBA processes with database-driven systems.
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Lead Software Engineer - Low Power Verification CadenceSAN JOSE $115k–$115k12d Lead Software Engineer improving performance and usability of UPF debug features for multi-billion-gate low-power designs on Palladium and Protium emulation platforms.
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DFT Design Engineer, ML Acceleration Annapurna-Labs-U-S-IncUSA $136k–$184k13d Design and optimize hardware for AWS Machine Learning inference and training servers (Inferentia and Trainium) by developing advanced Design for Test (DFT) architectures and ensuring silicon quality.
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VLSI Software Engineer↗ QualcommTijuana, BCN, MX 15d Develop internal CAD tools and methodologies for top-level chip floorplanning, RTL module placement, and datapath pipeline routing to optimize timing and area for Snapdragon chips.
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Research Engineer, AI for Chip Design OpenAISan Francisco 15d Build RL environments and evaluations to help AI models solve chip-design problems like RTL generation, design verification, and physical design optimization.
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Software Development Engineer↗ SiemensUP, IN 15d Develop and optimize compiler solutions and tools for Electronic Design Automation (EDA) applications to enable faster chip, board, and system design.
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Summer Program Intern↗ Marvell TechnologyCórdoba, X, AR 15d 10-week immersive summer program for engineering students to rotate through technical tracks in coherent optical technology.
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Summer Program Intern MarvellCordoba, Argentina 15d 10-week immersive summer program for engineering students to rotate through technical tracks in coherent optical technology.
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Systems Engineering Intern Texas InstrumentsDallas, TX, United States 15d Develop advanced analog and digital chips and system products from concept to mass production, including high-speed IC design cycles and system design activities.
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Layout Automation Developer Intern - 993 QuantinuumUS Brooklyn Park, MN 15d Develop Python and SKILL based automation tools to accelerate the physical layout of ion traps and related chips.
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Senior Engineer Design Enablement PDK GlobalFoundriesPenang 16d Develop, deploy, support, and maintain Process Design Kits (PDKs), techfiles, runtime code, and automation tools for Electronic Design Automation (EDA) tools to enable chip design.
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Technical Program Manager, Silicon/Hardware
MatXMountain View
$160k–$160k16d
Lead end-to-end execution of Silicon HW development programs from concept through tapeout, driving cross-functional teams to deliver performant and functionally accurate silicon for high-performance GenAI compute and memory management.
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AI Design Automation Engineer↗ AMDSan Jose, CA, US 16d Build AI-powered engineering platforms and backend data pipelines to help semiconductor design teams access, query, and leverage complex engineering data using natural language and knowledge graphs.
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Principal AI Engineer, SMAI↗ Micron TechnologyBoise, ID, US 16d Principal AI Engineer leading frontend manufacturing platform architecture and AI-assisted engineering practices for semiconductor fabrication operations.
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Senior PDK Support Engineer (Physical Verification) IntelUS, California, Santa Clara $174k–$330k16d Support Physical Verification (DRC/LVS/ERC/Density/LU) for Intel leading edge PDKs, performing PV runs, identifying violations, and implementing solutions.
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TEST SOLUTIONS ENGINEER MicronTaichung - Fab 16, Taiwan 16d Junior engineer developing DRAM test algorithms, probe test flows, and validation programs to improve yield and quality for memory products.
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Algorithm Design Engineer ON SemiconductorBangalore, Karnataka, India 17d Developing image processing algorithms that fit constraints related to technology, power, and area, including physical background modeling and data-mining approaches.
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Digital Design Flow Architect NxpAustin (Oakhill, Office), US 17d Define and deploy repeatable, traceable, and customizable end-to-end digital design flows for advanced process technologies, combining RTL-to-GDS implementation with AI tool enablement.
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EDA Software Engineer AlteraSan Jose, California, United States $149k–$149k17d Building scalable data models and high-performance APIs for FPGA device representation within Quartus Prime design software.
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Developer (Front End Infrastructure CAD Engineer)↗ EricssonAustin, TX, US $178k–$178k17d Develop, deploy, and support complex Electronic Design Automation (EDA) Software tools for ASIC, SoC, and FPGA IP design and verification.
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Design Enablement Engineer Intern PolarsemiBloomington, MN, USA $53k–$53k17d Intern role focused on establishing EDA/CAD environment scripting and automation to support product development and customer deliveries in the semiconductor industry.
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ASIC Design Automation Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $129k–$129k17d Develop, test, and deploy design automation software tools and flows for ASIC development, supporting IC hardware synthesis, place-and-route, and verification.
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IC CAD Layout Technician↗ QorvoBarcelona, CT, ES 18d Create and maintain IC CAD design data, generate GDSII layouts, and support tapeout activities for semiconductor manufacturing.
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C++ Senior R&D Engineer↗ SynopsysVancouver, BC, CA $100k–$100k18d Senior R&D engineer designing and building high-performance software solutions for chip design, verification, and IP integration tools.
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Senior Staff Engineer, CAD & Methodology Renesas-ElectronicsBengaluru, KA, in 18d Develop, deploy, and support scalable design automation infrastructure for Backend Physical Design teams to enable efficient RTL-to-GDSII implementation and signoff.
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