Hardware Verification
1,144 open positions
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Staff DFT Engineer AsteralabsIsrael 9d Design and implement Design-for-Test (DFT) architectures and strategies for next-generation AI connectivity chips to ensure silicon reliability and testability.
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Sr Engineer CAD Pre-Silicon Front End Velaura AISanta Clara, CA 9d Own front end automation carrying silicon from RTL entry to clean handoff into DFT and implementation.
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CAD RTL/FE Manager AppleJerusalem, Israel 9d Lead a team of ~20 engineers to develop software solutions for RTL design, integration, and static sign-off checks, while driving the transformation to AI and agentic workflows in chip design.
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Senior C++ Software Engineer↗ Tech Skills Resources (part of the Cpl Group)Limerick, County Limerick, Ireland 9d Design, develop, and optimize critical components for next-generation Electronic Design Automation (EDA) applications, focusing on high-performance computing and distributed systems.
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Senior R&D AI Software Development Engineer↗ Keysight TechnologiesYishun, North Region, Singapore 9d Develop agentic AI capabilities connecting LLMs, EDA applications, simulation engines, and user workflows to enable goal-driven automation for High-Speed Digital design tasks.
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Associate III - Semiconductor S/W Product Development↗ UstBengaluru, Karnataka, India 9d DevOps Automation Engineer supporting semiconductor software product development and SoC design.
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Senior CAD Engineer - Layout/Verification/Simulation MicronBoise, ID - Main Site, US $104k–$221k10d Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
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Stage - FPGA: benchmarking of open source tools f/m - Strategic Student Program Siemens-EdaMeudon, FRA, France €14k10d Develop a reproducible containerized benchmarking framework to evaluate open-source FPGA placement and routing tools on a large benchmark set.
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EDA Tools & Design Automation Engineer TenstorrentRemote $100k–$500k10d Own the deployment, configuration, reliability, and evolution of the EDA tool environment for mixed-signal design teams; develop and maintain AI-enabled design-automation tooling.
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Senior Manager, Digital Engineering Automation Renesas-ElectronicsBengaluru, KA, in 11d Lead the transformation of hardware engineering through automation, AI, reusable digital assets, and engineering knowledge platforms to modernize development practices.
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FPGA Development Tools - Intern↗ AlteraToronto, Ontario, Canada CA$95k–CA$100k11d Research, design, develop, and optimize software tools, compilers, flows, and frameworks for Field Programmable Gate Arrays (FPGA) acceleration.
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ASIC Design Automation Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $62k11d Develop, test, and deploy design automation software tools and flows to support IC hardware development, synthesis, place, route, and verification.
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Ingeniero/a Senior de Firmware (VHDL) y Documentación Técnica↗ Sopra SteriaMadrid, Community of Madrid, Spain 11d Senior Firmware Engineer specializing in VHDL code analysis, modification, and technical documentation for banking sector projects.
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Graduate Program - Engineering Pathways ArmMultiple locations £48k11d Graduate engineer contributing to real products and technical projects across hardware, software, AI, and systems at Arm.
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Computer Engineering↗ AlignerrRemote 11d Design advanced computer engineering challenges and author ground-truth solutions (assembly code, HDL, diagrams) to train AI models on hardware and systems topics.
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DSP Applications Engineer Advanced Micro Devices, IncOTTAWA, Canada 11d Drive customer adoption of AMD signal-processing technologies and build prototypes to help customers map workloads across AI Engines, programmable logic, CPUs, GPUs, and accelerators.
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Principal Engineer - Design Automation (EDA / CAD) Renesas ElectronicsIndia 11d Architect, develop, and deploy AI/ML and GenAI backend solutions for digital and analog chip design tools.
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Application Engineer II: Digital Design - Synthesis & Implementation Cadence SystemsBrasil 12d Application Engineer supporting customers in deploying Cadence's logical and physical implementation products (Synthesis, Place & Route, Signoff) for IC front and backend flows.
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QA Automation Engineer NR Consulting LLCUSA $103k–$143k12d Develop and execute comprehensive regression tests and test cases for full PDK Deck quality assurance, building robust processes and infrastructure for managing QA workflows and large volumes of generated test data.
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Senior Research Scientist, EDA and AI NVIDIAUS, CA, Santa Clara $192k–$305k12d Drive groundbreaking research at the intersection of AI, GPU computing, and Electronic Design Automation (EDA) to shape the future of chip design.
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FY27 Intern- AI-Driven Power Modeling for Evaluating Power Management Mechanisms in NoC Architectures - Guyancourt, 6 months QualcommGuyancourt, Yvelines, France 12d Build an AI/ML-based power modeling framework to estimate power consumption in Network-on-Chip (NoC) architectures during early design stages, enabling fast evaluation of power management mechanisms.
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CAD Design Enablement TPM EricssonAustin,Texas,United States 12d Consolidate engineering needs into a prioritized portfolio of initiatives and translate them into executable plans aligned with ASIC project milestones for Silicon CAD workflows.
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Senior VLSI Tools and Methodology Engineer HpeFt. Collins, Colorado, United States of America $140k–$321k12d Lead project teams and develop custom tools, flows, and methodologies to support the deployment of industry-standard EDA tools for complex VLSI design, validation, and testing.
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Staff CAD Engineer MarvellAustin, TX, US 12d Develop and maintain leading-edge Place and Route (P&R) flows and automated design tools for next-generation semiconductor chips.
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Design Application Engineering Intern (Summer 2027) GlobalFoundriesUSA - Texas - Austin 12d Support technical engagements from design concept through tape-out, translating customer requirements into technical recommendations and resolving design enablement issues.
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Software Engineer - Advanced↗ SiemensBurlington, MA, US $110k–$198k12d Develop and improve the emulator compiler software that maps customer System-on-Chip circuit designs onto emulation hardware resources.
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Software Engineer II: Hardware Job Scheduler R&D↗ Cadence Design SystemsBelo Horizonte, MG, BR 13d Develop and validate the Cadence Hardware Job Scheduler product for the Palladium emulation platform, which uses thousands of processors to emulate complex hardware designs and SoCs.
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Software Engineer II: Hardware Job Scheduler R&D↗ CadenceBelo Horizonte, Minas Gerais, Brazil 13d Develop and validate the Cadence Hardware Job Scheduler product for the Palladium emulation platform, which uses thousands of processors to emulate complex hardware designs and SoCs.
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Senior PDK Physical Verification Engineer IntelUS, Oregon, Hillsboro $150k–$285k13d Develop and deploy advanced density fill methodologies and Process Design Kit (PDK) solutions to ensure manufacturability and density compliance for Intel's advanced semiconductor technology nodes.
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Senior Software Engineer/ Application Developer (f/m/div) InfineonBelgrade 13d Design and develop the Infineon Design Flow infrastructure to reduce design cycle time and improve efficiency for semiconductor design teams.
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