EDA Tools Software Engineer
Core
Define process design rules, validate VLSI layouts, and develop CAD design content for Intel's next-generation process technology and products.
Role type
VLSI layout and verification engineer
Builds
VLSI layout designs, Tape-in Collaterals, and CAD design libraries for process development
Domain
Semiconductor manufacturing / VLSI design
Required skills
VLSI design, CAD, Python, C++, Semiconductor Device Physics, Silicon manufacturing flows, DRC, ICV, IC Validator, custom design and verification tools, debugging, flow development
Preferred skills
Semiconductor processing engineering, VLSI circuit mask design layout, solid-state physics, optics, IC process flow, UNIX/Linux platforms, Cadence Virtuoso, Klayout, Calibre DRV, Calibre
Technologies
Python, C++, Cadence Virtuoso, Klayout, Calibre DRV, Calibre, UNIX/Linux
Responsibilities
Verify VLSI layout adherence to complex layout design rules; Troubleshoot design and PDK verification issues with complex physical design flows; Write/update software code for cell design and testcases; Collaborate with Litho, Integration, Device, and OPC/RET experts to develop designs for process implementation
Seniority
Entry-level (0-1 years) or Junior
