FY27 Intern- AI-Driven Power Modeling for Evaluating Power Management Mechanisms in NoC Architectures - Guyancourt, 6 months
Core
Build an AI/ML-based power modeling framework to estimate power consumption in Network-on-Chip (NoC) architectures during early design stages, enabling fast evaluation of power management mechanisms.
Role type
Intern, Machine Learning Engineer (Hardware/NoC)
Builds
Automated characterization flow, reusable power dataset, benchmarked AI power models, and a prototype exploration tool for power-aware NoC architecture choices.
Domain
Semiconductor hardware design, Network-on-Chip (NoC), Low Power Design, Machine Learning
Deliverable
production ML models
Required skills
Python scripting, Machine Learning (ANN/MLP, Random Forest, GNNs), Power estimation tools (Synopsys PowerArtist/PrimePower), Digital design concepts, Traffic scenario modeling
Preferred skills
Verilog/VHDL, UVM, EDA flows, Bash
Technologies
Python, Synopsys PowerArtist, Synopsys PrimePower, NoC architectures, CDM, PCM
Responsibilities
Design control-plane NoC scenarios with power management IPs, run synthesis and timing simulations to extract switching activity, build a labeled dataset mapping parameters to power, train and compare ML models against gate-level references, use models for early design-space exploration.
Seniority
Intern
