CAD RTL/FE Manager
Core
Lead a team of ~20 engineers to develop and transform RTL/FE CAD tools, integrating agentic workflows and AI-assisted tooling into chip design flows for Apple products.
Role type
Senior IC Manager (RTL/FE CAD & Agentic Workflows)
Builds
Cloud-native CAD services, LLM harnesses for design triage, RTL connectivity tools, SoC assembly automation, and static sign-off check infrastructure.
Domain
Semiconductor / Chip Design / EDA
Deliverable
production ML models
Required skills
People leadership, RTL/FE CAD domain expertise, SystemVerilog/Verilog, static verification (Lint/CDC/RDC), software architecture, Python, cloud-native services, CI/CD, agile transformation
Preferred skills
Agentic workflows, LLM harness design, AI-assisted engineering, modern Python (AsyncIO/FastAPI), EDA vendor partnership
Technologies
Python, SystemVerilog, Verilog, Cloud-native, CI/CD, LLMs
Responsibilities
Lead and mentor a team of ~20 CAD engineers; Drive adoption of agentic workflows and AI-assisted design practices; Architect and execute LLM harnesses for RTL/FE flows; Own RTL integration and connectivity tooling; Manage static sign-off checks (Lint, CDC, RDC); Define strategic roadmaps aligned with tapeout milestones; Partner with EDA vendors and design teams; Champion software engineering best practices.
Seniority
Senior, hands-on IC with people leadership
