VLSI CAD Timing Intern, Applied AI - Summer 2027
Core
Develop end-to-end AI solutions for VLSI timing and constraint analysis workflows, spanning data generation, model training, orchestration, and agentic automation.
Role type
Summer intern, Applied AI for VLSI CAD
Builds
Intelligent systems for timing sign-off and constraint analysis
Domain
Semiconductor / VLSI Design / EDA
Deliverable
production ML models
Required skills
Static timing analysis (STA), VLSI/ASIC design, Python scripting, Data analysis, Agentic AI concepts, Digital design flows
Preferred skills
TCL, Machine learning, Physical design (floorplanning), Workflow automation
Technologies
PrimeTime, Tempus, Python, TCL
Responsibilities
Support static timing analysis flows, Automate timing and constraint validation flows, Analyze timing reports across corners and modes, Collaborate on timing sign-off strategies, Contribute to AI-assisted timing analysis approaches, Explore physical effects impact on timing
Seniority
Intern
