Senior PDK Physical Verification Engineer
Core
Develop and deploy advanced density fill methodologies and Process Design Kit (PDK) solutions to ensure manufacturability and density compliance for Intel's advanced semiconductor technology nodes.
Role type
Senior IC physical verification engineer (PDK/density fill)
Builds
Advanced PDKs and density fill solutions for Intel's most advanced technology nodes
Domain
Semiconductor manufacturing / Physical verification / Design automation
Required skills
Physical verification platforms (Calibre, ICV, Pegasus), Rule deck debugging (SVRF, TVF, PXL, PVL, Tcl), Density fill methodologies, Semiconductor process technology, Design rules, Unix/Linux environments, Algorithmic solutions for physical design
Preferred skills
Density fill at 16nm and below, Fill rule implementation, Process-aware design enablement, Custom layout environments (Virtuoso, Custom Designer), Cross-functional team leadership
Technologies
Calibre, Synopsys ICV, Cadence Pegasus, SVRF, TVF, PXL, PVL, Tcl, Unix/Linux, Cadence Virtuoso, Synopsys Custom Designer
Responsibilities
Lead development and validation of density fill solutions within advanced PDKs; Develop algorithmic solutions for physical verification platforms; Collaborate with process integration and design teams to define requirements; Drive automation initiatives for engineering efficiency; Design validation frameworks and test suites; Partner with external EDA vendors to deploy next-generation capabilities; Develop technical documentation and best practices.
Seniority
Senior, hands-on IC
