Staff DFT Engineer
Core
Design and implement Design-for-Test (DFT) architectures and strategies for next-generation AI connectivity chips to ensure silicon reliability and testability.
Role type
Staff DFT Engineer (Semiconductor)
Builds
Custom connectivity solutions for AI infrastructure (CXL, Ethernet, NVLink, PCIe, UALink)
Domain
Semiconductor / AI Infrastructure / Deep-submicron processes
Deliverable
production ML models
Required skills
DFT architecture definition, JTAG/iJTAG, MBIST, Scan, ATPG, Static Timing Analysis (STA), gate-level simulation, EDA tool proficiency (Synopsys TestMAX, Mentor Tessent), scripting (Tcl, Perl, Python, Shell), logic design, verification, debug
Preferred skills
High-speed interface protocol knowledge (PCIe, Ethernet, CXL, UALink), chip bring-up experience, mass production activities, advanced process technology experience (7nm and below)
