CAD RTL/FE Manager
Core
Lead a team of ~20 engineers to develop software solutions for RTL design, integration, and static sign-off checks, while driving the transformation to AI and agentic workflows in chip design.
Role type
Senior IC Manager (RTL/FE CAD)
Builds
RTL connectivity tools, SoC assembly automation, static sign-off check infrastructure (Lint, CDC, RDC), and cloud-native agentic services.
Domain
Semiconductor / Hardware Design Automation
Deliverable
production ML models
Required skills
People leadership, RTL design flow expertise, software architecture, Python, cloud-native services, CI/CD, EDA tool partnerships
Preferred skills
Agentic workflows, LLM harnesses, AI-assisted engineering, agile hardware transformation, distributed backend services
Technologies
Python, AsyncIO, FastAPI, Pydantic, SQLAlchemy, SystemVerilog, Verilog, Cloud
Responsibilities
Lead and mentor a team of ~20 CAD engineers; Drive adoption of agentic workflows and AI-assisted design practices; Own architecture of LLM harnesses for RTL/FE flows; Manage RTL integration and connectivity tooling; Define static sign-off check methodologies and metrics; Align roadmap with tapeout milestones; Partner with EDA vendors and design teams; Champion software engineering best practices.
Seniority
Senior, hands-on IC
