Senior CAD Engineer - Layout/Verification/Simulation
Core
Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
Role type
Senior IC CAD Engineer (Layout/Verification/Simulation)
Builds
Custom IC design flows, layout automation, physical verification, circuit simulation, and digital implementation tools.
Domain
Semiconductor / EDA / VLSI
Deliverable
production ML models | product features
Required skills
Python, SKILL, Tcl, Perl, C, C++, Linux/Unix shell scripting, CMOS/VLSI fundamentals, EDA tool integration, debugging, AI/ML for automation
Preferred skills
Cadence Virtuoso, Calibre DRC/LVS, Spectre/HSPICE/FineSim, Fusion Compiler/Innovus/PrimeTime, StarRC/Quantus, DRAM/HBM/NAND knowledge
Technologies
Cadence Virtuoso, Calibre, Spectre, HSPICE, FineSim, PrimeTime, Formality, StarRC, Quantus, Fusion Compiler, Innovus
Responsibilities
Develop and debug CAD tools and automation flows; Integrate and qualify EDA tools in production; Partner with design and verification teams to resolve workflow challenges; Identify tool gaps and evaluate industry offerings; Provide training and production support; Apply AI/ML to engineering workflows; Mentor engineers and lead technical projects.
Seniority
Senior, hands-on IC
