Senior CAD Engineer - Layout/Verification/Simulation
Core
Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
Role type
Senior IC CAD engineer (layout/verification/simulation)
Builds
EDA tool flows and automation for custom memory and storage ICs
Domain
Semiconductor / VLSI / EDA
Deliverable
production ML models | product features
Required skills
Python, SKILL, Tcl, Perl, C, C++, Linux/Unix shell scripting, CMOS/VLSI fundamentals, EDA tool integration, debugging, technical mentorship
Preferred skills
Cadence Virtuoso, Calibre DRC/LVS, Spectre/HSPICE/FineSim/PrimeSim/VCS/Xcelium, Fusion Compiler/Innovus/PrimeTime/Formality, StarRC/Quantus, AI/ML for engineering workflows, source control, automated testing, DRAM/HBM/NAND knowledge
Technologies
Cadence Virtuoso, Calibre, Spectre, HSPICE, FineSim, PrimeSim, VCS, Xcelium, Fusion Compiler, Innovus, PrimeTime, Formality, StarRC, Quantus, Python, SKILL, Tcl, Perl, C, C++
