Senior SoC Digital Verification Engineer, Multimedia Lab
Core
Building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users.
Role type
Senior IC SoC digital verification engineer (multimedia)
Builds
Video codec hardware accelerators for advanced video encoding and processing
Domain
Semiconductor / Video Compression
Deliverable
production ML models
Required skills
SystemVerilog, UVM methodology, Constrained Random Verification, Directed Testing, Gate-Level Simulation (GLS), SDF back-annotated timing simulation, Python/Perl/Shell scripting, Debugging and logical analysis
Preferred skills
Hardware Emulation (Palladium, ZeBu), FPGA prototyping, Formal Verification, SoC-level Performance and Power-Aware (PA) verification
Technologies
VCS, Incisive, Questa, Verdi, Palladium, ZeBu, JasperGold
Responsibilities
Develop comprehensive module-level, subsystem-level, or SoC system-level Test Plans; Build and maintain highly reusable and automated advanced verification environments (Testbench) and components; Develop high-quality testcases and drive Functional and Code Coverage to 100% closure; Assist in FPGA prototyping and Hardware/Software co-debugging on Emulation platforms; Develop and maintain regression testing scripts and automation tools to improve verification efficiency.
Seniority
Senior, hands-on IC
