SoC Digital Verification Engineer, Multimedia Lab
Core
Develop and maintain automated verification environments and test plans for video codec hardware accelerators (FPGA/ASIC) to ensure functional and timing closure.
Role type
SoC Digital Verification Engineer
Builds
Video codec hardware accelerators for encoding and processing
Domain
Semiconductor / Video Compression
Required skills
SystemVerilog, UVM methodology, Constrained Random Verification, Directed Testing, Gate-Level Simulation, SDF back-annotation, Python/Perl/Shell scripting, Debugging
Preferred skills
Hardware Emulation (Palladium/ZeBu), FPGA prototyping, Formal Verification, SoC Performance and Power-Aware verification
Technologies
VCS, Incisive, Questa, Verdi, Palladium, ZeBu, JasperGold
Responsibilities
Develop comprehensive Test Plans for module, subsystem, and SoC levels; Build and maintain reusable automated verification environments (Testbench, Scoreboard, Monitor, Sequence); Execute Constrained Random and Directed tests to achieve 100% coverage; Perform Gate-Level Simulation and timing simulation; Optimize regression testing scripts and automation tools.
Seniority
Mid-level, hands-on IC
