芯片DFT工程师（芯片平台） - 芯片研发
Core
Design and implement DFT solutions for SoC chips, covering scan, MBIST, ATPG, and boundary scan, while collaborating on timing/power-IR analysis and post-silicon ATE test debugging.
Role type
DFT engineer (SoC design)
Builds
SoC chips with integrated DFT and testability features
Domain
Semiconductor / Chip Design
Required skills
DFT methodologies (Scan, MBIST, ATPG, Boundary Scan), EDA tool proficiency, scripting (TCL, Perl, Python), timing/power-IR analysis, post-silicon ATE test debugging
Preferred skills
Synthesis, Static Timing Analysis (STA)
Technologies
DFT EDA tools, TCL, Perl, Python, ATE
Responsibilities
Implement DFT strategies for SoC chips, collaborate on timing and power convergence, debug and optimize ATE test vectors and coverage
Seniority
Mid-level, hands-on IC
