Senior Software Engineer- AI for RTL Design & Formal Verification
Core
Develop and deploy AI-driven agents and LLM-powered tooling to accelerate RTL design, physical design, static analysis, and formal verification workflows for next-generation semiconductor products.
Role type
Senior IC software engineer (AI/ML for EDA)
Builds
AI-assisted engineering assistants, multi-turn dialogue systems, agentic AI solutions for design verification, and design databases/dashboards.
Domain
Semiconductor industry + AI/ML for Electronic Design Automation (EDA)
Deliverable
production ML models
Required skills
Python, LLMs (fine-tuning, multi-agent systems, RAG), vector databases, RTL design languages (Verilog/SystemVerilog), formal/static verification tools
Preferred skills
EDA/CAD flow optimization, formal property verification, assertion-based verification (SVA), static timing/lint tools, CI/CD practices
Technologies
LLMs, agentic frameworks, RAG pipelines, vector databases, JasperGold, VC Formal
Responsibilities
Design and deploy AI applications using LLMs to support RTL and formal verification flows; build infrastructure for LLM-powered engineering assistants; develop agentic AI solutions for bug triage and proof convergence; maintain design databases combining agentic and deterministic retrieval; collaborate with RTL design and verification teams to translate pain points into AI tooling.
Seniority
Senior, hands-on IC
