VLSI IP Characterization Engineer, Senior to Staff
Core
Characterize VLSI IP (standard cells, memory, IO) using EDA tools and simulation models to support front-end design flows and silicon validation.
Role type
Senior to Staff IC VLSI IP Characterization Engineer
Builds
IP characterization data, statistical variation models, and design kits (DK) for Qualcomm ASIC products
Domain
Semiconductor / VLSI / ASIC Design
Required skills
CMOS/FinFET logic knowledge, digital circuit design optimization, standard cell/memory/IO circuit knowledge, IP characterization, Python/Perl scripting, UNIX/Linux, logical problem-solving, analytical debugging
Preferred skills
Industrial EDA tool automation, data analysis/visualization, Liberty formats (CCS, LVF), statistical variation models, front-end pre-silicon design flow, RTL/Verilog/SystemVerilog, SVA, DFT/BIST, Static Timing Analysis, physical design, SPICE simulation, DRC/LVS/ERC
Technologies
Python, Perl, UNIX/Linux, EDA tools, Liberty formats, SPICE, Verilog, SystemVerilog
Responsibilities
Characterize IP blocks using EDA tools and simulation models; Develop and maintain statistical variation models and design kits; Automate EDA workflows and data analysis; Collaborate on front-end design flows and silicon validation
Seniority
Senior to Staff, hands-on IC
