Engineer/Staff Engineer – Chip Physical Verification CAD
Core
Define and deliver physical sign-off flows and solutions for SoC design at advanced process nodes.
Role type
Staff Engineer, Chip Physical Verification CAD
Builds
Physical verification flows, DRC/LVS/ANT/DMY/ERC/LPE/ESD rule decks, layout implementation flows
Domain
Semiconductor, SoC Design, Physical Verification
Required skills
DRC/LVS/ANT/DMY/ERC/LPE/ESD rule deck development, layout implementation flow design, full-chip physical verification debugging, automation scripting (C-shell, Python, Perl), AI/LLM application for verification productivity
Preferred skills
AI techniques for script generation, defect triage optimization
Technologies
C-shell, Python, Perl, LLM
Responsibilities
Code and maintain rule decks for various processes, develop layout and physical verification flows, collaborate with QA to reduce PDK/Rule deck defects, perform full-chip physical verification and debugging, implement automation scripts, explore AI techniques to improve verification productivity
