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Package Design Methodology Engineer

US, CA, Santa Clara💼 Full-time💰 $136,000–$136,000🗓 2026-09-29

Core

Design and implement VLSI tools and methodologies to construct, analyze, and validate multi-die package designs for NVIDIA's next-generation AI and HPC platforms.

Role type

Senior IC EDA tooling engineer (package design)

Builds

Production-grade EDA tooling and automated design flows for multi-die packages

Domain

Semiconductor packaging / VLSI / AI Hardware

Deliverable

production ML models | product features

Required skills

Python, C++, VLSI package design, interposer design, IC physical design, signal integrity, power delivery, parasitic extraction, data structures, algorithms, object-oriented design

Preferred skills

AI/ML techniques in engineering workflows, LLMs for code generation, ML-assisted design analysis

Technologies

Python, C++, EDA environments

Responsibilities

Design and implement VLSI tools for silicon and substrate design; Develop applications to enable project engineers with an emphasis on maintainability; Develop flows/tools to construct, analyze, and validate package designs; Optimize daily workflows of package designers

Seniority

Senior, hands-on IC

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