Staff Implementation Engineer
Core
Senior Physical Design Engineer responsible for end-to-end RTL-to-GDSII implementation of complex CPU, GPU, interconnect, and SoC designs.
Role type
Senior IC physical design engineer (SoC/Processor)
Builds
Sophisticated processor cores, graphics units, communication fabrics, and SoC builds
Domain
Semiconductor / ASIC Physical Design
Required skills
RTL-to-GDSII physical implementation, MCMM timing closure, floorplanning, placement and congestion optimization, clock tree synthesis, routing, power integrity, low-power implementation (UPF, power gating), scripting (Tcl, Python, Perl, shell)
Preferred skills
High-performance Arm CPU/GPU implementation, sophisticated process nodes, hierarchical physical design, structured clock architectures, foundry/EDA vendor collaboration
Technologies
Tcl, Python, Perl, shell, Make, UPF, STA, EDA tools
Responsibilities
Own end-to-end RTL-to-GDSII physical implementation, drive timing closure across MCMM scenarios, own physical implementation readiness and signoff closure, debug complex implementation and EDA-tool issues, develop and improve implementation methodologies and automation
Seniority
Senior, hands-on IC
